The invention relates generally to integrated circuits and, in particular, to device structures for field-effect transistors and methods of forming device structures for a field-effect transistor.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type field-effect transistors (PFETs) and n-type field-effect transistors (NFETs) that are coupled to implement logic gates and other types of integrated circuits, such as switches. Field-effect transistors generally include an active semiconductor region, a source and a drain defined in the active semiconductor region, and a gate electrode associated with a channel in the active semiconductor region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current.
Silicon-on-insulator (SOI) substrates may be advantageous in CMOS processes. In comparison with field-effect transistors built using a bulk silicon wafer, an SOI substrate permits transistor operation at significantly higher speeds with improved electrical isolation and reduced electrical losses. Contingent on the thickness of the device layer of the SOI substrate, a field-effect transistor may operate in a partially-depleted mode in which the depletion layer in the channel in the device layer does not extend fully to the buried oxide layer when typical control voltages are applied to the gate electrode.
Improved device structures for field-effect transistors and methods of forming device structures for a field-effect transistor are needed.